1. Field of the Invention
The present invention relates to a digital signal processing chip, and more particularly, to a circuit for controlling execution of a loop in a digital signal processing chip which can prevent an error from being generated when the number of loop executions is zero, shorten the execution time upon realization of an entire algorithm, and reduce waste of a program memory.
2. Description of the Related Art
A digital signal processing chip is used a lot in fields necessary for a large amount of arithmetic calculation, i.e., an audio codec, echo canceling, etc. In the algorithms of these fields, many portions use a loop. Here, there is a case when a loop is executed a fixed number of times, but in many cases, the loop is repeated a variable number of times. Most of the digital signal processing chips input the number of loop executions to a control register, and then a designated section is repeated by the input number. Also, when a loop is repeated the variable number of times, a case when zero is input as the number of loop executions frequently occurs. At this time, an existing digital signal processing chip executes a loop once, and then the value of the control register is arbitrarily changed, thus generating an error. That is, the conventional digital signal processing chip generates an error when the number of loop executions is zero, i.e., when zero is input to the control register in which the number of loop executions is input. To be more specific, when the number of loop executions is zero, a loop is executed once, and then the control register has a maximum of its value, thus generating an error. In order to prevent the generation of the errors, the conventional digital signal processing chip always must perform a routine for checking whether the number of loop executions is zero in the case that the loop is repeated a variable number of times.